1. Field of the Invention
The present invention relates to a pixel electrode contact structure of a liquid crystal display device and, more particularly, to a pixel electrode contact structure of a thin film transistor (TFT) liquid crystal display device.
2. Description of Related Art
Currently, since the cost for photolithography in the process for manufacturing the liquid crystal display panel is very high, manufacturers do their best to reduce the number of the lithography cycles in the manufacturing process to minimize costs. So far, the average number of the photolithography cycle (or the number of the mask cycle) has been reduced to about 4 or 5. However, some disadvantages happen on the contact interface between the pixel electrode and the conductive lines for connecting the drain of the TFT on the substrate of the panel in the optimized manufacturing processes.
The equivalent circuit of a single pixel on the TFT LCD panel can be seen in FIG. 1. As shown in FIG. 1, the pixel includes elements such as a transistor 1, a pixel electrode 2, a storage capacitor 3, source lines Vs, scan lines Vg, and a common line Vcs. In most cases, the projection of the source lines on the panel intersects with that of the scan lines. The common lines are arranged parallel to the scan lines. The source, gate, and drain are electrically connected with the source lines, the scan lines, and the pixel electrode respectively. The drain is electrically connected with the storage capacitor, too. As the transistor 1 is turned on, the currents from the source lines can pass to the pixel electrode 2 for displaying and to the storage capacitor 3 for further storing. The charge stored in the capacitor 3 is released to supplement the charge on the pixel electrode 2 to retain the voltage as the transistor 1 is turned off. Hence, the possibility for dark spots or bright dots to occur can be reduced.
However, owing to the conventional contact structure of the prior arts, some bright dots or some dark spots still occur. The conventional process for manufacturing the transistor area of a thin film transistor liquid crystal display device (TFT-LCD) panel can be seen in FIG. 2a. As shown in FIG. 2a, a gate metal 10 is formed on a glass substrate 20 first. Then, a gate insulating layer 30 is formed on the top of the gate metal 10. Subsequently, a patterned amorphous silicon layer 50a, and a patterned semi-conductive ohmic layer 50b are formed on the gate insulating layer 30. Finally, a patterned layer composed of a Ti layer 40b and an Al layer 40a is deposited on the semi-conductive ohmic layer 50b. In general, the Ti layer 40b is sandwiched between the Al layer 40a and the semi-conductive ohmic layer 50b. After the metal layers are formed, a second insulation layer 70 and an organic resin layer 80 are formed on the top for covering the layer illustrated above. Then a pixel electrode layer 90 such as ITO and optionally a passivation layer (not shown) are formed on the top of the organic resin layer 80.
As the process for manufacturing the TFT is undergoing, the pixel electrode contact area is formed through similar process at the same time so as to minimize costs. The structure of the conventional pixel electrode contact area can be seen in FIG. 2b. As shown in FIG. 2b, the gate metal 10 formed on the glass substrate 20 is used as a bottom electrode of a capacitor (i.e. storage capacitor). However, the amorphous silicon 50a and the semi-conductive ohmic layer 50b in TFTs cannot be seen in the conventional pixel electrode contact area. In other words, the amorphous silicon and the semi-conductive ohmic layer are removed in the conventional pixel electrode contact area. Moreover, the pixel electrode 90 electrically connects the Al layer 40a through the via 60 located in the second insulation layer 70 and the organic resin layer 80. The Ti layer 40b and the Al layer 40a in this pixel electrode contact area function as a composite top electrode of a capacitor (i.e. storage capacitor) together. In fact, the composite top electrode of a capacitor is the same as or extended from the composite laminate of the drain in the transistor. However, in most of the cases, the materials of the pixel electrode such as ITOs are electrochemically active to the Al layer 40a. Hence, a reaction frequently occurs on the interface of the pixel electrode contact area. The product of this reaction results in a high electrical resist in the pixel electrode contact area, and further interferes with the driving of the motion of the liquid crystal molecules.
For improving the high electrical resist on the interface of the pixel electrode contact area, another contact structure is presented and made. The suggested contact structure can be seen in FIGS. 3a and 3b. FIG. 3b shows a cross section view of the line area marked as A-A′ in FIG. 3a. The TFT of the liquid crystal display device of FIGS. 3a and 3b is the same as that illustrated in FIG. 2a. However, in the pixel electrode contact area, the patterned amorphous silicon layer 50a, and a patterned semi-conductive ohmic layer 50b are used as buffer layers for etching in via 60. The buffer layers are shown in the inside area circled by the dash line 60a in FIG. 3a. As the via 60 is formed, a part of the patterned amorphous silicon layer 50a and the patterned semi-conductive ohmic layer 50b in the pixel electrode contact area are removed by trough etching. Hence, the pixel electrode layer (ITO) will contact the gate insulating layer 30 directly. Moreover, the pixel electrode layer (ITO) also contacts the Ti layer 40b in the lateral part because of the undercut formed on the Al layer 40a by over etching.
As shown in FIG. 3a, as the patterned amorphous silicon layer 50a and the patterned semi-conductive ohmic layer 50b are formed on the gate insulating layer 30, the area inside the square 50 will keep a square-shaped patterned amorphous silicon layer 50a and a square-shaped patterned semi-conductive ohmic layer 50b. Then a patterned Ti layer 40a and a patterned Al layer 40b are formed in the area 40. Next, a second insulation layer 70 and an organic resin layer 80 are formed to cover the layers illustrated above. Finally, an etching for the area circled by the dash line 60a is performed to form via or a contact hole 60. In most of the etching steps for forming contact hole or via, over etching is frequently used for guaranteeing the exposure of the gate metal layer 10. But the over etching will also reduce the thickness of the gate insulating layer 30. Even with the existence of the aforesaid buffer layers (i.e. amorphous silicon layer 50a and semi-conductive ohmic layer 50b), some spikes or bumps still generate on the surface of the gate insulating layer 30, and a current leakage will occur to result in the deactivation or malfunction of the storage capacitor.
Therefore, it is desirable to provide an improved method to mitigate the aforementioned problems.